The present invention relates in general to integrated circuits, and in particular to a an improved lock-detect circuit for systems using phase-locked loops.
A phase-locked loop (PLL) is a circuit that operates to bring the phase of the output signal of a voltage-controlled oscillator (VCO) in alignment with that of a reference input signal. One common application for PLLs is in frequency synthesizers where a stable reference input clock is used to generate different frequencies. A conventional PLL includes a phase comparator that receives the reference input signal and the output of the VCO, and detects a phase difference therebetween. The error signal that represents the phase difference at the output of the phase comparator is then filtered and applied to the VCO to control its output frequency. By adjusting the phase of the VCO output signal in response to the magnitude of the phase error signal, this servo loop operates to minimize the error signal and to lock the phase of the reference signal with that of the input signal.
A PLL may fail to phase-lock and/or frequency-lock to the reference input frequency under several conditions. Some of these conditions are part of the normal operation and happen at expected times such as during the acquisition, or frequency transition modes. Other conditions are not part of the normal operation and are often unpredictable. These include loss of lock due to loss of input signal or significant degradation of the quality of the input signal (e.g., excessive jitter or modulation).
In many applications, it is crucial for the system to know at all times whether the system clock, which is usually generated by a PLL, is in lock condition in order to ensure data integrity. Hence, a lock-detect circuit becomes necessary.
Of the various lock-detect circuits that have been proposed, some require large frequency counters to monitor the frequency of the reference input signal and the signal at the output of the VCO divider. These schemes consume large area of silicon and power, and are only for frequency lock detection, not phase lock detection. Further, existing lock-detect circuits typically do not address the failure to lock situation when the reference frequency disappears or deviates significantly from the intended frequency.
There is therefore a need for an area and power efficient implementation of a lock-detect circuit that operates reliably under all conditions.